基于CPLD的含倍频器的数字频率计.docVIP

基于ＣＰＬＤ的含倍频器的数字频率计 目录 引言················································２页 方案设计············································３页 总体设计············································５页 单元电路及软件模块设计······························６页 单元电路测试······································１５页 附录··············································１６页 参考文献·········································２０页 一、引言 基于CPLD的数字频率计设计，它由锁相环倍频器、及基于CPLD的测频单元两部分组成，可以将待测频率放大一百倍之后通过测频单元，由于CPLD往往存在一个波形的误差，将待测频率放大一百倍后，误差变为以前的百分之一，这样就大大提高了测频计的精度。传统的频率计直接测量低频的待测频率，精度不高，本设计改善了这点。 本设计达到的技术要求：（1）在0Hz~400Hz时倍频器能将输入信号倍频一百倍；（2）倍频器的误差范围±0.5Hz；（3）测频计有两个四联排的数