基于LBDL逻辑的抗DPA攻击电路设计方法.PDFVIP

31 6 JOURNAL OFNATIONAL UNIVERSITYOF DEFENSE TECHNOLOGY Vol.31 No.6 2009 :1001- 2486(2009) 06- 0018- 07 X LBDL DPA 乐大珩, 李少青, 张民选 ( , 410073) : (DPA) ( Look-Up-Table, LUT) (LBDL), , WDDL(Wave Dynamic Differential Logic) ,LBDL , WDDL , DPA : ; DPA ; :TN43112 :A An LBDL Based VLSI Design Method to Counteract DPA Attacks YUE Da-heng,LIShao-qing,ZHANG Min-xua (Parallel and Distributed Processing Laboratory, NationalUniv. of DefenseTechnology, Changsha 410073, China) Abstract:Dynamic and differential logic styles are proposed as a typical differential power analysis (DPA) resistant technology. Becauseof the constant transitio nrate of dynamic and differential logic gates, the correlatio nbetwee npower consumptio nand signal values is significantlyreduced. Inthis paper, anovel look-up-table(LUT) based differential logic( LBDL) and thedesig nmethod based o nthis logic arepresented. Instead of afull custom design, this method combines somemodificatio nwith a regular standard cell desig flow. Thus, havea betterpracticability. UnlikeWDDL (Wave DynamicDifferentialLogic), which ca nalso be implemented by standard cell desig nflow, thetransitio ntimeof LBDL gates is independent of input values, hencepower consumptio nof LBDL is moreconstant. Experimental results indicatethat the LBDL-based desig nmethod ca neliminates most of the power leakage. Key words: security chip; DPA attack; dynamic and differential logic CMOS , ,P. Kocher [1] (Differential PowerAnalysis,DPA) , , , DPA 1999, DPA , , DPA , , , Kris Tiri