考虑NBTI的动态休眠管尺寸电源门控设计-论文.pdfVIP

Vol No JOU RNA L OF H EFEI U NIV ERSIT Y O F T EC HNOL OGY M ar DOI issn j N B T I complementary metal oxide semiconductor CM OS ow er gating PG p negative bias temperature instability NBT I Header PG sleep transistor ST NBT I PG PG NBT I NBT I PG PG NBT I ST ST ST ST PG ST ST PG HSPICE PG NBT I ST T N A NBTIaware power gating design based on ST dynamic oversizing Y U A N Ye YI M aoxiang Z HA N G Lin GA N Yingxian H U A N G Zhengf eng X U Hui School of Elect ro nic Science and A pplied Phy sics H ef ei U niv er sity of T echnology H ef ei China Colleg e of Co mput er Sci ence and Engineering A nhui U niv er sity of Science and T echnology H uainan China Abstract For nanometer scale complementary metal oxide semiconductor CM OS integ rated circuit design using the pow er gating PG technology to reduce static pow er dissipation has become a main stream trend With the shrinking of integ rated circuit technology size the circuit aging eff ect induced by negative bias temperature instability NBT I is getting w orse When a Headerty pe PG circuit is in operative mode the PM OS sleep transistor ST is negatively biased and w ill suff er serious NBT I eff ect resulting in circuit perf ormance lo ss T hrough the analy sis of the NBT I induced PG circuit ag ing a model to predict the NBT Iaw are perf ormance lo ss of PG circuit is proposed By grouping the ST s a method in w hich the ST groups are opened discontinuously to dy namically adjust the ST size or it s onres