I2C各个子程序r.docVIP

-- Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifos -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; package I2C is component simple_i2c is port ( clk : in std_logic; ena : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(7 downto 0); -- 4x SCL -- input signals start, stop, read, write, ack_in : std_logic; Din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; Dout : out std_logic_vector(7 downto 0); -- i2c signals SCL : inout std_logic; SDA : inout std_logic ); end component simple_i2c; end package I2C; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity simple_i2c is port ( clk : in std_logic; ena : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(7 downto 0); -- 4x SCL -- input signals start, stop, read, write, ack_in : std_logic; Din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; Dout : out std_logic_vector(7 downto 0); -- i2c signals SCL : inout std_logic; SDA : inout std_logic ); end entity simple_i2c; architecture structural of simple_i2c is component i2c_core is port ( clk : in std_logic; nReset : in std_logic; clk_cnt : in unsigned(7 downto 0); cmd : in std_logic_vector(2 downto 0); cmd_ack : out std_logic; busy : out std_logic; Din : in std_logic; Dout : out std_logic; SCL : inout std_logic; SDA : inout std_logic ); end component i2c_core; -- commands for i2c_core constant CMD_NOP : std_logic_vector(2 downto 0) := 000; constant CMD_START : std_logic_vector(2 downto 0) := 010; constant CMD_STOP : std_logic_vector(2 downto 0) := 011; constant CMD_READ : std_logic_vector(2 downto 0) := 100; cons