cordic算法的Verilog实现.docVIP

cordic算法的Verilog实现 cordic算法的Verilog实现 283 module cordic #(parameter DATA_WIDTH=8) ( input clk, input rst_n, input ena, input [DATA_WIDTH-1:0] phase_in, output reg [DATA_WIDTH-1:0] sin_out, output reg [DATA_WIDTH-1:0] cos_out, output reg [DATA_WIDTH-1:0] eps ); localparam PIPELINE=8; reg [DATA_WIDTH-1:0] phase_in_reg; reg [DATA_WIDTH-1:0] x0,y0,z0; reg [DATA_WIDTH-1:0] x1,y1,z1; reg [DATA_WIDTH-1:0] x2,y2,z2; reg [DATA_WIDTH-1:0] x3,y3,z3; reg [DATA_WIDTH-1:0] x4,y4,z4; reg [DATA_WIDTH-1:0] x5,y5,z5; reg [DATA_WIDTH-1:0] x6,y6,z6; reg [DATA_WIDTH-1:0] x7,y7,z7; reg [1:0] quadrant [PIPELINE:0]; integer i; always @(posedge clk,negedge rst_n) begin if(!rst_n) phase_in_reg = 8b0; else if(ena) begin case(phase_in[7:6]) 2b00: phase_in_reg = phase_in; 2b01: phase_in_reg = phase_in-8h40; 2b10: phase_in_reg = phase_in-8h80; 2b11: phase_in_reg = phase_in-8hc0; default:; endcase end end always @ (posedge clk,negedge rst_n) begin if(!rst_n) begin x0=8b0; y0=8b0; z0=8b0; end else if(ena) begin x0 = 8h4D; //0.60725*2^7 y0 = 8h00; z0 = phase_in_reg; end end //level 1 always @ (posedge clk,negedge rst_n) begin if(!rst_n) begin x1 =8b0; y1 =8b0; z1 =8b0; end else if(ena) if(z0[7]==1b0) begin x1 = x0-y0; y1 = y0+x0; z1 =z0-8h20;//45deg end else begin x1=x0+y0; y1=y0-x0; z1=z0+8h20; end end //level 2 always @ (posedge clk,negedge rst_n) begin if(!rst_n) begin x2 =8b0; y2 =8b0; z2 =8b0; end else if(ena) if(z1[7]==1b0) begin x2 = x1-{y1[DATA_WIDTH-1],y