基于流水线技术的AES算法的FPGA优化和验证.doc

基于流水线技术的AES算法的FPGA优化与验证 摘要 AES自从被接纳为标准之日起已经被工业界、银行业和行政部门作为事实上的密码标准。为了获得AES算法在面积和速度上的优化，本Based on the AES algorithm pipelining optimization and verification of FPGA Abstract AES has been accepted as the standard since the date has been the industrial sector, banking and administration as the de facto standard for passwords. AES algorithm in order to obtain the design in the FPGA area and speed optimization, the design on the one hand on the wheel function operator to optimize the use of look-up table method optimized byte substitution operation, column mixing operations and key expansion operation. On the other hand the hardware structural optimization for high-speed parallel implementation using AES encryption algorithm structure - inside and outside the hybrid pipeline structure and gives the overall design diagram; last and designed to do other similar transverse contrast, concluded that: This design guarantees based on the speed and the speed of the balance of resources, the performance has a great advantage. This design uses a top-down design ideas, use the code QUARTUS II development tools and comprehensive preparation of the compilation and simulation results are given. Keywords: AES, FPGA optimization, internal and external mixing, pipeline 目录 摘要 I Abstract II 第一章 绪论 2 1.1 课题背景 2 1.1.1 密码学简介 2 1.1.2 高级数据加密标准简介 2 1.2 课题任务 3 第二章 AES算法介绍和优化 4 2.1 AES算法介绍 4 2.1.1 字节替换(SubBytes) 4 2.1.2 行移变换(ShiftRows) 5 2.1.3 列混合变换(MixColumns) 6 2.1.4 密钥加法(AddRoundKey) 6 2.1.5 密钥扩展(ExpandedKey)和选取 6 2.2 算法优化 8 2.2.1 S-盒查表优化 8 2.2.2 列混合变换优化 9 2.2.3 密钥扩展优化 9 2.3 算法评价 9 第三章 AES算法加密系统实现 10 3.1 加密系统结构设计 10 3.1.1 循环展开结构 10 3.1.1 流水线结构 11 3.2 加密系统的模块设计 13 3.2.1 数据单元 13 3.2.2 密钥扩展模块 14 3.2.3 控制模块 15 第四章 AES加密系统FPGA设计和仿真验证 16 4.1 开发环境和工具 16 4.2 系统的仿真和验证 16 第五章 结论 19 参考文献 21 致谢 22 第一章 绪论 1.1 课题背景 1.1.1 密码学简介 随着计算机与通信技术的迅猛发展，大量敏感信息通过公用通信设施和计算机网络进行交换。信息的安全、高效的传输成为当前的迫切需要。密码学能够很好的解决数据机密性保护和身份认证等方面的难题。 密码学广泛应用于通信安全保密和存储加密等领域。密码学的基本思想是对机密信息进行交换，以保护信息在传送过程中不被非法