我的集成电路基础_7.pptVIP

Digital Integrated CircuitsA Design Perspective Sequential Logic In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edge-triggered elements flip-flops This leads to confusion however Latch versus Register Latches 2、动态与静态 3、功能 Clocked inverter operation （4） TSPC Including Logic in TSPC (2) 基于静态CMOS门的锁存器 Static latch based on simple gate Cross-Coupled NAND (3) Mux-Based Latches 基于选择器的锁存器 三、 Flip-flops Master-slave flip-flop （２） C2MOS （２）Master-Slave (Edge-Triggered) Register 四、Design of Seque