音响IC资料-TDA1305T.pdf

INTEGRATED CIRCUITS DATA SHEET TDA1305T Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2) Preliminary specification 1995 Dec 08 Supersedes data of September 1994 File under Integrated Circuits, IC01 Philips Semiconductors Preliminary specification Stereo 1fs data input up-sampling filter with TDA1305T bitstream continuous dual DAC (BCC-DAC2) FEATURES • Easy application • 16fs Finite-duration Impulse-Response (FIR) filter incorporated • Selectable system clock (f ) 256f or 384f sys s s 2 • I S-bus serial input format (at f = 256f ) or LSB fixed sys s 16, 18 or 20 bits serial input mode (at f = 384f ) sys s • Slave-mode clock system • Cascaded 4-stage digital filter incorporating 2-stage FIR bitstream converter for low signals while large signals are filter, linear interpolator and sample-and-hold generated using the dynamic continuous calibration technique, thus resulting in low power consumption, small • Smoothed transitions before and after muting chip size and easy application. (soft mute) The TDA1305T is a dual CMOS DAC with up-sampling • Digital de-emphasis filter for three sampling rates of filter and noise shaper. The combination of high 32 kHz, 44.1 kHz and 48 kHz