数字costas环verilog设计代码.docxVIP

//数字costas环,设计使用在GPS信号的跟踪部分//环路噪声带宽Bl=160Hz//修改时间:2016/6/6//modelsim仿真通过//diff_data有正有负,修正pre_uct为有符号数module costas (input clk, rst,input track_block,//阻塞环路变化,避免初始uct过大input sink_valid,input signed [7:0] sink_data,input [21:0] phi_inc,//捕获输入的精细频率output reg costas_lock,//costas环的锁定信号output reg signed [7:0] sine_value,//输出同步正弦载波output [9:0] mt//输出解调后的信息);//-------------------------------------------wire out_valid;wire [15:0] fsin_o, fcos_o;reg signed [17:0] uct;//-------------------------------------------NCO部分//-------------------------------------------8位数据宽度,16位频率调制宽度costas_nco costas_nco0(.phi_inc_i(phi_inc),//f0=1557kHz.clk(clk),.reset_n(rst),.clken(1b1),.freq_mod_i(uct),//频率控制字.fsin_o(fsin_o),.fcos_o(fcos_o),.out_valid(out_valid));//-------------------------------------------NCO的输出仅在out_valid有效时有效//-------------------------------------------做一级缓存，将不平滑的数据平滑reg signed [7:0] cosine_value;//-------------------------------------------将16位的数据截断为8位always @(posedge clk or negedge rst)if(!rst)beginsine_value = 0;cosine_value = 0;endelse if(out_valid)begincosine_value = fcos_o[15:8];sine_value = fsin_o[15:8];end//-------------------------------------------wire signed [15:0] mul_if, mul_qf;//-------------------------------------------计算两个乘法assign mul_if = sink_data * sine_value;assign mul_qf = sink_data * cosine_value;//-------------------------------------------reg mul_valid;reg signed [7:0] mul_i, mul_q;//-------------------------------------------always @(posedge clk or negedge rst)if(!rst)beginmul_valid = 0;mul_i = 0;mul_q = 0;endelse if(sink_valid)beginmul_valid = 1;mul_i = mul_if[14:7];mul_q = mul_qf[14:7];endelsemul_valid = 0;//-------------------------------------------wire lpf_valid;wire signed [7:0] lpf_i, lpf_q;//-------------------------------------------低通滤波器滤除2倍频分量costas_lpf costas_lpf_i//I路(.clk(clk),.reset_n(rst),.ast_sink_data(mul_i),.ast_sink_valid(mul_valid),.ast_source_ready(1b1),.ast_sink_error(2b00),.ast_source_data(lpf_i),.ast_sink_ready(),//NC.ast_s