高性能数字乘法器芯片电路设计.doc

高性能数字乘法器芯片电路设计 摘 要 高性能乘法器是现代数字信号处理器(DSP)中的重要部件，是完成高性能实时数字信号处理和图像处理的关键所在。浮点乘法器具有面积大、延迟长、结构复杂的特点。如何设计出高速、简单且结构规则的浮点乘法器成为广泛关注的问题。过去的十年中，研究者扩展了Booth编码算法的空间，提高了乘法器的性能；改进了部分积压缩技术，使乘法器结构更加规则；以传输管逻辑、多路选择器和动态技术为基础的各种电路实现方法也持续刷新高性能乘法器的实现记录；与此同时，与物理实现紧密相关的乘法器拓扑结构的研究也硕果累累。但不断提高的高性能运算需求使得高性能乘法器的设计和实现仍然是当前的热门话题。 本文从延迟、面积、结构复杂性等方面系统地研究了乘法部件的各个过程。在研究了乘法器Booth编码算法，乘法器部分积压缩拓扑结构和高速求和等算法的基础上，分析比较乘法器各部分的不同实现方法，设计了一个高性能的16位浮点并行乘法器。该乘法器的指数部分与尾数部分并行运算，缩短了关键路径；采用修正Booth编码缩减了部分积数量；采用结构规整的(4：2Carry、Sum Design of Digit and High-speed multiplier IC Circuit Abstract High performance multiplier is the important component of the digital signal processor，the key to implement the signal processing and image processing；Multiplier always has large area, long latency and complex structure．It becomes attractive how to design a fast，simple and regular multiplier．In the past ten years，researchers have developed new Booth algorithm to improve the performance of the multiplier；eveloped many formal compress trees to make the structure of the multiplier more regular；mplement the circuits using pass-transistor logic，multiplexer, dynamic method and so on；he topology of multiplier, which related with physical implementation closely，also developed very rapidly．However，the desire for high performance computation makes the design of multiplier not come to the end． Based on the work in designing a floating-point multiplier in the 16 bit floating point DSP, this dissertation gives a systematic research on the every stages of the multiplier considering delay, area and complex．Based on the study of Booth algorithm，multiplier topology, and the final adder, this thesis introduces and compares kinds of multipliers，implemented a 16 bit high performance parallel multiplier, the exponent and mantissa of which compute in parallel way ,modified Booth algorithm and(4：2) compress tree are used to generate and calculate the partial products．arry select adder sums the final two partial products；Character vectors and random vector