Modeling with Verilog A英文文献.pdfVIP

Introduction Jiao Chao Tsinghua University Feb. 2006 All Right Reserved Verilog-A overview A simple example Verilog-A solution How to describe the system structure? How to describe the component behavior? Use Verilog-A in Cadence All Right Reserved An IEEE standard analog hardware description language. Designed for modeling the behavior of analog components. Verilog-A is a procedural language, with constructs similar to C and other languages Many EDA software provider support Verilog-A, such as Cadence, Angilent, Silvaco, Mentor and so on. All Right Reserved Verilog-A is a subset of Verilog-AMS (Analog Mixed Signal) All Right Reserved OVI -- Open Verilog International Verilog-A is a circuit design oriented HIGH level language. Enables compact modeling engineer to easily develop proprietary SPICE models for specific semiconductor technology behavior. If compile-complete, the simulation speed is close to built-in C-based models. Compiled code is in binary format and transporting this code will protect the users IP. All Right Reserved typedef struct SPICEdev { IFdevice DEVpublic; int (*DEVparam)(); /* routine to input a parameter to a device instance */ // Diode Model int (*DEVmodParam)(); /* routine to input a paramater to a model */ int (*DEVload)(); /* routine to load the device into the matrix */ `include constants.vams int (*DEVsetup)(); /* setup routine to preprocess devices once */ int (*DEVunsetup)(); /* clean up before running again */ `include disciplines.vams int (*DEVpzSetup)(); /* setup routine for pz analysis */ int (*DEVtemperature)(); /* tempera