synopsys学习资料-cy7c1463av33_5.pdf

CY7C1461AV33 CY7C1463AV33 PRELIMINARY CY7C1465AV33 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture Features • JTAG boundary scan for BGA and fBGA packages • Burst Capability—linear or interleaved burst order • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Low standby power • Can support up to 133-MHz bus operations with zero Functional Description[1] wait states — Data is transferred on every clock The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1-Mbit x 36/2-Mbit x 18/512K x 72 Synchronous Flow • Pin-compatible and functionally equivalent to ZBT™ -through Burst SRAM designed specifically to support devices unlimited true back-to-back Read/Write operations without the • Internally self-timed output buffer control to eliminate insertion of wait states. The CY7C1461AV33/CY7C1463AV33/ the need to use OE CY7C1465AV33 is equipped with the advanced No Bus Latency • Registered inputs for flow-through operation (NoBL) logic required to enable