数据库 ch5_5m.ppt

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Synthesis Simulation Agenda Overview Concurrent Statements Sequential Statements Where? Agenda Overview Concurrent Statements Signal Assignment WHEN-ELSE WITH-SELECT-WHEN Sequential Statements C Language void main() { int F;int A = 1;int B = 0;int C = 0;int D = 1; F = A D; // F = 1 A = B C; // A = 0, F = 1 } Concurrent Statements Example library ieee; use ieee.std_logic_1164.all; --------------------------------- entity TS is port (B, C, D : buffer std_logic; F : out std_logic ); end TS; --------------------------------- architecture TS_arch_0 of TS is signal A : std_logic; begin F = A and D; -- The value of A is not “old” A = B and C; -- The value of A is updated end TS_arch_0; Concurrent Statement Property All the Concurrent Statement is executed in parallel Concurrent Statement does not care the position within the coding Concurrent Statement is : OUTPUT depends on INPUT only Agenda Overview Concurrent Statements Signal Assignment Delay Resolution Function WHEN-ELSE WITH-SELECT-WHEN Sequential Statements Signal Assignment SignalName = [Options] Expression [after TimeExpression], Expression [after TimeExpression], ... ; Inertial Delay Example A = B nand C after 0.2 ns; H = 00, 01 after 10 ns, 10 after 20 ns; Property of The Inertial Delay Inertial means that pulses shorter than the delay are ignored. Example B = A after 20 ns; (Pulse narrower than 20 ns will not be sent to B) Transport Delay Transport means that the assignment acts as a pure delay line Example B = A transport after 20 ns; (Pulse shorter than 20 ns will also be sent to B) Agenda Overview Concurrent Statements Signal Assignment Delay Resolution Function WHEN-ELSE WITH-SELECT-WHEN Sequential Statements Resolution Function (Example) library ieee;use ieee.std_logic