数据库 ch9_8_2m.pptVIP

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Simulation Synthesis Agenda Design Tips Example Analysis Speed Bottleneck in Sequential Logic Balance of The Combinatorial Logic Blocks Pipeline For Speed Save Synthesis Time Drive Problem? Shadow Register Drive Problem? Buffer Control Delay Setup Hold Time Maybe Too Fast To Satisfy Setup/Hold Time Extra Delay Between DFFs Clock Enable Clock Skew Bad Clock Good Clock Ripple Clock Parallel Clock Glitch (1) Glitch (2) Asynchronies Clock (1) Asynchronies Clock (2) Asynchronies Clock (3) Retiming (1) Retiming (2) State Machine Model A Better State Machine Models Dissimilar FFs (Bad Code) Dissimilar FFs (Good Code) Parentheses Speed Make It Simple Case-when HW Unintentional Latches If-else-then ? HW * * ? ? D Q CLK DCLK tsetuo thold Clock Input Q_A/D_B Q_B Hold time for D_B ? D Q Enable D Q Enable Synchronized by CLK_B Edge detection is synchronized by 20M_CLK library ieee;use ieee.std_logic_1164.all;entity badFFstyle isport ( clk : in std_logic; rst_n : in std_logic; d : in std_logic; q2 : out std_logic);end badFFstyle; architecture rtl of badFFstyle issignal q1 : std_logic;begin process (clk) begin if (clkevent and clk = 1) then if (rst_n = 0) then q1 = 0; --q2???  else q1 = d; q2 = q1; end if; end if; end process;end rtl; library ieee;use ieee.std_logic_1164.all;entity goodFFstyle isport ( clk : in std_logic; rst_n : in std_logic; d : in std_logic; q2 : out std_logic);end goodFFstyle;architecture rtl of goodFFstyle is signal q1 : std_logic;begin process (clk) begin if (clkevent and clk = 1) then if (rst_n = 0) then q1 = 0; else q1 = d; end if; end if; end process; process (clk) begin if (clkeve