数据库 ch9_8_2m.pptVIP

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Simulation Synthesis Agenda Design Tips Example Analysis Speed Bottleneck in Sequential Logic Balance of The Combinatorial Logic Blocks Pipeline For Speed Save Synthesis Time Drive Problem? Shadow Register Drive Problem? Buffer Control Delay Setup Hold Time Maybe Too Fast To Satisfy Setup/Hold Time Extra Delay Between DFFs Clock Enable Clock Skew Bad Clock Good Clock Ripple Clock Parallel Clock Glitch (1) Glitch (2) Asynchronies Clock (1) Asynchronies Clock (2) Asynchronies Clock (3) Retiming (1) Retiming (2) State Machine Model A Better State