[工学]321Hello World on the Nios II platform Cyclone III FPGA.pdfVIP

Tutorial 1: Hello World on the Nios II platform, Cyclone III FPGA 1 1 Tutorial 1: Hello World on the Nios II platform, Cyclone III FPGA Overview This tutorial will demonstrate how to generate hardware and related software interfaces in the form of RTL (Register Transfer Logic) HDL descriptions and software system libraries appropriate for use with the Altera Quartus II, SOPC Builder, and Nios II IDE software tools. The sample project will implement a trivial Hello World application. This sample project includes a software process (running on the Nios II processor) and a hardware process (running in the FPGA) that communicate via a single stream over the Avalon bus. Onchip memory inside the FPGA is sufficient for accommodating the Hello World executable file. The purpose of this tutorial is to take you through the entire process of generating hardware and software interfaces and importing the relevant files to the Altera environment. The tutorial will also describe how to create the platform and downloadable FPGA bitmap using the Altera tools. Finally, you will learn how to build and run an Impulse C software application on the Nios II processor using the Nios II IDE. The hardware platform used in this tutorial is Altera Cyclone III Evaluation Kit, featuring Altera Cyclone III EP3C25 FPGA, and a touch-screen LCD display. This tutorial will require approximately 90 minutes to complete, including software run times. Steps Loading the Hello World Application Compiling the Application for Simulation Building the Application for the Target Platform Exporting Files from CoDeveloper Creating a Quartus Project