[工学]第5章_VHDL设计进阶.pptVIP

数控分频器1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity f_div is port ( clk:in std_logic; d :in std_logic_vector(7 downto 0); fout:out std_logic ); End entity f_div; architecture behave of f_div is signal fInner : std_logic; begin process(clk) variable count :integer range 0 to 255; begin if (clk=1 and clkevent) then if count=d then count:=0; else count:=count+1; end if; if(count CONV_INTEGER(d) /2)then fInner =0; else fInner =1; end if; end if ; end process; fout = fInner ; end architecture behave; if (clk=1 and clkevent) then if count=d then count:=0; else count:=count+1; end if; if(count CONV_INTEGER(d) /2)then fInner =0; else fInner =1; end if; end if ; 数控分频器2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity f_div is port ( clk:in std_logic; d :in std_logic_vector(7 downto 0); fout:out std_logic ); End entity f_div; architecture behave of f_div is signal full : std_logic; begin Count:process(clk) variable count :std_logic_vector(7 downto 0); begin if (clk=1 and clkevent) then if count= then count:=d; full = ‘1’; else count:=count+1; full = ‘0’; end if; end if ; end process Count; Div: process(full) variable cnt2: std_logic; begin if full’event and full= ‘1’ then cnt2 := not cnt2; if cnt2 =‘1’ then fout = ‘1’; else fout= ‘0’; end if; end if; end process div; end architecture behave; 多路选择器－－基于并行条件赋值语句 library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux21 is port ( in1,in2 : in std_logic; sel : in std_logic; sout : o