基于VHDL的频率计设计论文.docVIP

JIU JIANG UNIVERSITY 毕 业 论 文（设 计） 题 目 基于VHDL的频率计设计 英文题目 The frequency meter based on VHDL design 院 系 电子工程学院 专 业 电子信息工程 姓 名 年 级 指导教师 2015年6月 摘 要 数字频率计是直接用十进制数字来显示被测信号频率的一种测量装置。它不仅可以测量正弦波、方波、三角波、尖脉冲信号，而且还可以测量它们的周期。经过改装，可以测量脉冲宽度，做成数字式脉宽测量仪；在电路中增加传感器，还可以做成数字脉搏仪、计价器等。因此数字频率计在测量物理量方面应用广泛。本设计用VHDL在CPLD器件上实现数字频率计测频系统，能够用十进制数码显示被测信号的频率，而且还能对其他多种物理量进行测量。具有体积小、可靠性高、功耗低的特点。采用VDHL编程设计实现的数字频率计，除被测信号的整形部分、键输入部分和数码显示部分以外，其余全部在一片FPGA芯片上实现，整个系统非常精简，而且具有灵活的现场可更改性。 关键字：VHDL语言；频率计；FPGA The frequency meter based on VHDL design Abstract Digital frequency meter is directly with a decimal number to display the measured signal frequency of a measuring device. It not only can measure the sine wave, square wave, triangle wave, pulse signal, but also can measure their cycle. Modified, and can measure pulse width, into a digital pulse width measuring instrument; Add the sensors in the circuit, but also can be made into digital pulse apparatus, meter, etc. So the digital frequency meter has been widely applied in measuring physical quantities. This design with VHDL on the CPLD device to realize digital frequency meter frequency measurement and control system, can use decimal digital display measured signal frequency, but also to measure a variety of other physical quantities. With the characteristics of small volume, high reliability, low power consumption. VDHL programming design was adopted to realize digital frequency meter, in addition to the measured signal of the plastic part and digital display, key input parts, all on a FPGA chip, the whole system is very compact, and with flexible field is modified. Key Words：VHDL language; Frequency meter; FPGA 目 录 摘 要 I The frequency meter based on VHDL design II Abstract II 第一章 绪论 1 1．1课题的研究背景 1 1．2频率计发展现状 1 第2章 数字频率计的要求 3 2.1