[工学]第二部分 VHDL的模型.pptVIP

卢庆莉 编写 例一： library ieee; use ieee.std_logic_1164.all; entity eqcomp4 is port ( a ,b : in std_logic_vector(3 downto 0); equals : out std_logic); end eqcomp4; Architecture behavioral of eqcomp4 is Begin comp:process(a ,b) begin if a=b then equals = ‘1’; else equals =‘0’; end if; end process comp; End behavioral ; 二、结构描述(structural descrip