fpga在电力电子技术powerelectronics中的应用.docVIP

FPGA在电力电子技术（power electronics）中的应用 Quartus2的使用方法（pwm控制作成） 非常简单的语言实现硬件pwm控制 新工程（开关频率198khz分解能8bit） File-new project wizard 一路输入next下去(工程名pwm198khz) toplever entity部分(block) file-new 然后选择 block diagram/schematic file 然后save as，名字要和工程名相同。不同的时候,不能compilation 文件是pwm198khz.bdf.这个相当于你工作的顶层模块 1.3变调波作成 1.3.1 sin波的地址vhdl作成 File-new，选择vhdl file --address3960 -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity address3960 is port( CLOCK , RESET : in std_logic ; address_data1 : out std_logic_vector(11 downto 0)); end address3960 ; architecture rtl of address3960 is signal CLK1 : std_logic ; -------------------------------internal_clock signal count_f_counter : std_logic_vector(16 downto 0) ; signal count_CLK: std_logic_vector(8 downto 0) ; -----------internal_signal_9bits signal count_dat：std_logic_vector(11 downto 0) ; -----------internal_signal_12bits begin ---Counter---------------------------------------------------------------------------- process (CLOCK,RESET) begin if (RESET = 1) then count_CLK=000000000; --------------------------9bits_o CLK1 = 0 ; elsif (CLOCKevent and CLOCK = 1) then if (count_CLK 111110011) then ------------------9bits_499 count_CLK = count_CLK + 1; clk1=0; elsif (count_CLK = 111110011 ) then --------------499 count_CLK = 000000000; clk1=1; end if; end process; ---Calling_rom_address------------------------------------------------------------ process (CLK1,RESET) begin if (RESET = 1) then count_data1 = 000000000000 ; ------------------------------8bits_0 elsif (CLK1event and CLK1 = 1) then if (count_data1 111101110111) then -----------------------8bits_3959 count_data1 = count_data1 + 1; elsif (count_data1 = 111101110111 ) then -------------------8bits_3959 count_data1 = 000000000000;