EPM570芯片手册.doc

■ Chapter 1, Introduction ■ Chapter 2, MAX II Architecture ■ Chapter 3, JTAG and In-System Programmability ■ Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices ■ Chapter 5, DC and Switching Characteristics ■ Chapter 6, Reference and Ordering Information Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. I–2 Section I: MAX II Device Family Data Sheet ? October 2008 Altera Corporation MAX II Device Handbook 1. Introduction Introduction The MAX? II family of instant-on, non-volatile CPLDs is based on a 0.18-μm, 6-layermetal- flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control. Features The MAX II CPLD has the following features: ■ Low-cost, low-power CPLD ■ Instant-on, non-volatile architecture ■ Standby current as low as 29 μA ■ Provides fast propagation delay and clock-to-output times Revision History MAX II Device Handbook ? October 2008 Altera Corporation ■ UFM block up to 8 Kbits for non-volatile storage ■ MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V ■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels ■ Bus-friendly architecture including programmable slew rate, drive strength, bushold, and programmable pull-up resistors ■ Schmitt triggers enabling noise tolerant inputs (programmable per pin) ■