FPGA程序加法器.docVIP

顶层设计程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JIA is PORT(clockin: in std_logic; resetin:in std_logic; kbin : in std_logic_vector(3 downto 0); kbout : out std_logic_vector(2 downto 0); segment_out : out STD_LOGIC_VECTOR(6 downto 0); sweepout : out STD_LOGIC_VECTOR(3 downto 0)); end JIA; architecture Behavioral of JIA is COMPONENT keyboard is port(clk,reset : in std_logic; kb_in : in std_logic_vector(3 downto 0); c,d: out std_logic_vector(3 downto 0); seg1,seg2 : out std_logic_vector(6 downto 0); swo,so: out std_logic; kb_out : out std_logic_vector(2 downto 0)); END COMPONENT; COMPONENT add is port ( a,b: in std_logic_vector(3 downto 0); s1,s2: in std_logic; s: out std_logic_vector(4 downto 0)); END COMPONENT; COMPONENT yima is port(Clock,reset : in std_logic; seg3,seg4 : out std_logic_vector(6 downto 0); sin: in std_logic_vector(4 downto 0)); END COMPONENT; signal e,k: STD_LOGIC; signal f,g : std_logic_vector(3 downto 0); signal h : std_logic_vector(4 downto 0); signal segment_out1 : STD_LOGIC_VECTOR(6 downto 0); signal segment_out2 : STD_LOGIC_VECTOR(6 downto 0); signal segment_out3 : STD_LOGIC_VECTOR(6 downto 0); signal segment_out4 : STD_LOGIC_VECTOR(6 downto 0); type state_type is (z0,z1,z2,z3); signal state: state_type; signal div:std_logic_vector(26 downto 0):=(others=0); signal clk:std_logic; BEGIN process(clockin) begin if rising_edge(clockin) then div=div+1; if div=79999 then div=(others=0); end if; if div=39999 then clk=1; else clk=0; end if; end if; end process; process(clk) begin if(clkevent and clk=1) then case state is when z0=state=z1; when z1=state=z2; when z2=state=z3; when z3=state=z0; end case; end if; end process; u1: keyboard PORT MAP(clk=clockin,kb_in=kbin,r