[信息与通信]基于VHDL语言的数字频率计的设.docVIP

基于VHDL语言的数字频率计的设计 摘要 数字频率计是近代电子技术领域的重要测量工具之一，同时也是其他许多领域广泛应用的测量仪器。随着技术的发展，传统的自下而上的数字电路的设计方法、工具、器件已远远落后于当今技术的发展。传统数字频率计由于在高频段受基准时钟频率的限制而测频精度受到限制,该测频系统的设计扬弃了传统的自下而上的数字电路设计方法，采用先进的EDA技术及自上而下的设计。把资源丰富、控制灵活及良好人机对话功能的AT89C51单片机为系统的主控部件，实现整个电路的测试信号控制、数据运算处理、键盘扫描和控制数码管的显示输出。具有内部结构重组、现场可编程的CPLD芯片EPM7128SLC84-15实现各种时序逻辑控制、计数功能。在MAX+plusⅡ平台上，用VHDL语言编程完成了CPLD的全部编程设计。在AT89C51单片机控制下，闸门信号开启时，被测信号经过放大、整形后与系统提供的50MHZ基准时钟信号同时送入CPLD的两个输入端计数。当闸门信号关闭时，CPLD内的两套32位计数器同时停止计数，单片机将计数器的计数值分为四次读入其内存进行运算处理，并将结果输出显示。通过对8只按键的选择，对输入信号频率，方波信号宽度及高、低电平的占空比进行测试。该系统很好地整合了单片机控制的灵活性与CPLD芯片现场可编程性的优点，不但大大缩短了开发研制周期，而且使本系统具有结构紧凑、体积小，并且测频范围宽、精度高、可靠性高。 关键词 :频率计;CPLD;VHDL;单片机 Abstract The digital frequency meter is one of modern electronic technology domain important measuring tools, simultaneously is also other many domain widespread application metering equipment. Along with the technical development, the traditional digital circuits design method, the tool, the component from bottom to top fell behind by far now the technical development. Traditional digit frequency meter as a result in high frequency band datum clock rate limit, but the frequency measurement precision is restricted, this frequency measurement systems design has developed the good and discard the bad the traditional digital circuit design method from bottom to top, uses the advanced EDA technology and the top-down design. Fruitful in resources, control nimble and good man-machine conversation function AT89C51 monolithic integrated circuit for systems master control part, realizes the entire electric circuits spike control, data operation processing, the keyboard scanning and the control nixietube demonstration output. Has the internal structure reorganization, scene programmable CPLD chip EPM7128SLC84-15 to realize each kind of sequential logic control, the tally function. In MAX+plusⅡIn the platform, has completed the CPLD complete programming design with the VHDL language programming. When AT89C51 monolithic integrated circuit