FPGA发挥部分程序.docVIP

`timescale 1ns / 1ps /*//////第一、二种方法/////// module half_adder( output sum, output carry, input a, input b ); assign sum=a^b;//xor A1(sum,a,b); assign carry=ab;//and B1(carry,a,b); endmodule /////////////////////*/ /*//////第三种方法 /////// module half_adder( output reg sum, output reg carry, input a, input b ); always @(a,b)begin sum=a^b; carry=ab; end endmodule */ /*//////第四种方法/////// module half_adder( output reg sum, output reg carry, input a, input b ); always@(a,b) begin {carry,sum}=a+b; end endmodule */ //第五种方法； module half_adder( output reg sum, output reg carry, input a, input b ); always@(a,b) begin case({a,b}) 2b00:begin carry=0;sum=0;end 2b01:begin carry=0;sum=1;end 2b10:begin carry=0;sum=1;end 2b11:begin carry=1;sum=0;end endcase end initial begin // Initialize Inputs a = 0;b = 0;#100; a = 0;b = 1;#100; a = 1;b = 0;#100; a = 1;b = 1;#100; end module full_adder( output reg [3:0]sum, output reg carry, input [3:0]a, input [3:0]b, input ci ); always@(a,b,ci) begin {carry,sum}=a+b+ci; end endmodule initial begin // Initialize Inputs a = 0; b = 0; ci = 0; #100; for(x=0;x=2000;x=x+1) begin {a,b,ci}={a,b,ci}+1;#100;end end 2－4 4－2编译码器及拼接 `timescale 1ns / 1ps module coder2_4(out,in ); output reg [3:0]out; input [1:0]in; always@(in) begin if(in==2b00)out=4b0001; else if(in==2b01)out=4b0010; else if(in==2b10)out=4b0100; else if(in==2b11)out=4b1000; else out=4bx; end endmodule module decoder4_2(out,in ); output reg [1:0]out; input [3:0]in; always@(in) begin if(in==4b0001)out=2b00; else if(in==4b0010)out=2b01; else if(in==4b0100)out=2b10; else if(in==4b1000)out=2b11; else out=2bx; end endmodule module aa(out,in); input [1:0]in; output [1:0]out; wire [3:0]w; coder2_4 aaa (.out(w), .in(in)); decoder4_2 bbb (.out(out), .in(w)); endmodule module decoder38(Y,A,B,C,G1,G2a,G2b