EDA基于VHDL的乐曲播放电路设计报告.docVIP

乐曲播放电路设计 乐曲播放电路顶层电路图 二、模块和源程序 1、分频模块 分频顶层电路 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity yourname_div is port(clk50mhz:in std_logic; clk5mhz:buffer std_logic; clk1khz:out std_logic); end entity; architecture behav of yourname_div is signal clk50khz:std_logic; begin process(clk50mhz) variable cnt:integer range 0 to 9; begin if(clk50mhzevent and clk50mhz=1) then if cnt9 then cnt:=cnt+1; clk5mhz=0; else cnt:=0;clk5mhz=1; end if; end if; end process; process(clk5mhz) variable cnt1:integer range 0 to 99; begin if(clk5mhzevent and clk5mhz=1) then if cnt199 then cnt1:=cnt1+1; clk50khz=0; else cnt1:=0;clk50khz=1; end if; end if; end process; process(clk50khz) variable cnt2:integer range 0 to 49; begin if(clk50khzevent and clk50khz=1) then if cnt249 then cnt2:=cnt2+1; clk1khz=0; else cnt2:=0;clk1khz=1; end if; end if; end process; end behav; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_div2 is port(clk:in std_logic; q:out std_logic); end yourname_div2; architecture rtl of yourname_div2 is begin process(clk) variable cnt:std_logic_vector(0 downto 0); begin if clkevent and clk=1 then if cnt1 then cnt:=cnt+1; else cnt:=(others=0); end if; end if; if cnt=1 then q=1; else q=0; end if; end process; end rtl; 2、music_tone 模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity yournamemusic_tone is port(cs:in std_logic; index:in std_logic_vector(3 downto 0); code:out std_logic_vector(3 downto 0); high:out std_logic_vector(3 downto 0); tone:out std_logic_vector(10 downto 0)); end entity; architecture one of yournamemusic_tone is signal index1:integer range 0 to 15; signal tone1:integer range 0 to 2047; signal code1:integer range 0 to 15; begin index1=conv_integer(index); tone=conv_std_logic_vector(tone1,