晶片封装指南.pdfVIP

Maxim App Notes GENERAL ENGINEERING TOPICS PROTOTYPING AND PC BOARD LAYOUT Keywords: Wafer Level Package, WLP, Flip Chip, Flip-Chip, CSP, Chip Scale Package, PCB Assembly, PCBA, Die Product, Silicon Oct 18, 2004 Circuit, Silicon Die Circuit APPLICATION NOTE 3377 Maxim Wafer-Level Package Assembly Guide Abstract: Wafer-Level Packaging (WLP) allows an integrated circuit (IC) to be attached to a printed-circuit board (PCB) face- down, with the chips pads connecting to the PCB pads through individual solder balls. This document describes the packaging technique and its advantages. It describes printed-circuit board (PCB) layout and assembly process development for Maxim WLP. Wafer-Level Packaging (WLP) uses individual solder balls to connect the integrated circuit (IC) to a printed-circuit board (PCB). The IC is mounted face-down. This technology differs from other ball-grid array, leaded, and laminate based CSPs because there are no bond wires or interposer connections. The principle advantage is that IC-to-PCB board inductance is minimized. Secondary benefits are reduction in package size and manufacturing cycle time, and enhanced thermal conduction characteristics. This document describes printed-circuit board (PCB) layout and assembly process development for Maxim WLP. Note that it is intended for initial PCB layout design and assembly process development and does not assume any reliability objective for the customer end product. Customers still need to qualify their specified end product life reliability requirements. Package Construction Maxim Package Outlines The WLP solder bump interconnect is manufactured by building-up on a silicon wafer substrate. A film of BCB (Benzocyclobutene) resin is applied over the wafer circuit surface. This film provides mechanical stress relief for the ball attachment and electrical isolation at the die surface. Vias are imaged in the BCB film, providing electrical contact to the IC bon