网站大量收购独家精品文档,联系QQ:2885784924

官方说明书ANALOG DEVICES AD5065 数据手册.pdf

  1. 1、本文档共28页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
官方说明书ANALOG DEVICES AD5065 数据手册

Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP AD5025/AD5045/AD5065 FEATURES ence buffer is provided on chip. The AD5025/AD5045/AD5065 Low power dual 12-/14-/16-bit DAC, ±1 LSB INL incorporate a power-on reset circuit that ensures the DAC output Individual voltage reference pins powers up zero scale or midscale and remains there until a valid Rail-to-rail operation write takes place to the device. The AD5025/AD5045/AD5065 4.5 V to 5.5 V power supply contain a power-down feature that reduces the current consump- Power-on reset to zero scale or midscale tion of the device to typically 400 nA at 5 V and provides software Power down to 400 nA @ 5 V selectable output loads while in power-down mode. The parts are 3 power-down functions put into power-down mode over the serial interface. Total unad- Per channel power-down justed error for the parts is 2.5 mV. The parts exhibit very low Low glitch upon power-up glitch on power-up. The outputs of all DACs can be updated Hardware power-down lockout capability simultaneously using the LDAC f

文档评论(0)

qiwqpu54 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档