ADS线性低噪放LNA的设计.pdfVIP

Lab 1 Linear LNA design Objective: 1. Obtaining the FET Model from the manufacturer website 2. Operating point using DC trace 3. Bias circuit design 4. Noise Circle and Input matching 5. Output matching for maximum gain 6. Final matching network design FET Model We will use a PHEMT FET from Agilent technology. The part number is ATF54143. We can download the model zap file (the proprietary zip file for ADS project) from the Agilent website (/USeng/nav/- 536893727.536886206/pd.html). Download the model file (ATF54143.zap). Unarchive the zap file as shown. Create a new project and name it LNA_training. Click OK. Open Latest54143.dsn design from the ATF54143_prj directory. We need to save this design into our project directory so that we can use it as ATF54143 model in our simulation. Choose Save As from File menu and Click save. DC Tracing 1. Create a new schematic 2. Choose FET biasing template 3. Insert the FET model from the library list. Click on Library as shown. The library window will show up Click on Latest54143 Sub-networks. Back to the schematic window, place ATF54143 into the DC Tracing template The VI-curve from ATF54143 datasheet shows that Vgs is about 0.3 to 0.7 V. (ATF54143 is a PHEMT FET. It requires positive Vgs) Hence, we set the DC tracing parameters as shown and connect D to Drain, G to Gate, S1 to GND and S2 to GND. Simulate the circuit by clicking . 0.4 SIM1.VGS=1.000 0.3 SIM1.VGS=0.900 SIM1.VGS=0.800 i 0.2 . S SIM1.VGS=0.700