CPLD课程设计交通灯程序.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; Entity jiaotongdeng is port( clk_in:in std_logic; --4MHz rst:in std_logic; --复位信号 light:out std_logic_vector(7 downto 0); --RYG_main,RYG_gene spk:out std_logic; LED7S0:out STD_LOGIC_VECTOR(6 downto 0); LED7S1:out STD_LOGIC_VECTOR(6 downto 0); LED7S2:out STD_LOGIC_VECTOR(6 downto 0); LED7S4:out STD_LOGIC_VECTOR(6 downto 0) ); end jiaotongdeng; architecture arc of jiaotongdeng is type states is(green_red,yellow_red,red_green,red_yellow); signal state:states:=green_red; signal nextstate:states; signal data0:integer range 0 to 9; signal data1:integer range 0 to 9; signal data2:integer range 0 to 9; signal data3:integer range 0 to 9; signal clock_buffer:std_logic; signal count_time:integer range 0 to 1999999; signal clk:std_logic; signal sec0:integer range 0 to 9; signal sec1:integer range 0 to 3; signal sec2:integer range 0 to 9; signal sec3:integer range 0 to 3; BEGIN spk=0; frequent:process(clk_in) begin if clk_inevent and clk_in=1 then if count_time=1999999 then count_time=0; clock_buffer=not clock_buffer; else count_time=count_time+1; end if; end if; clk=clock_buffer; --输入1HZ的频率 end process; light_statment:process(state) --交通信号灯的显示状态 begin case state is when green_red=light nextstate=yellow_red; data0=5; data1=0; data2=5; data3=0; when yellow_red=light nextstate=red_green; data0=4; data1=2; data2=9; data3=2;