FPGA时钟显示QuartusⅡ程序代码.docVIP

--FPGA时钟显示QuartusⅡ程序代码 --epm240芯片已验证可使用 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shzh is port(res:in std_logic; clk:in std_logic; dataout:out std_logic_vector(7 downto 0); en:out std_logic_vector(3 downto 0)); end shzh; architecture arr of shzh is signal data1,data2,data3,data4,data_temp:std_logic_vector(3 downto 0); signal en_xhdl:std_logic_vector(3 downto 0); signal count:integer range 0 to signal clk_data:std_logic; begin en=en_xhdl; process(clk,count) variable cnt_scan:std_logic_vector(15 downto 0); begin if clkevent and clk=1