基于vhdlpoc设计说明书.docxVIP

The Report of POC DesignMarch 29, 20111、Purpose1. The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer.2.The use of MaxPlus II for design and simulation.2、Taska. The physical model of POCPOC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices). Figure 1 Printer Connectionshows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol illustrated in. Figure2 The handshake-timing diagram between POC and the printerb.The logical model of POCThe handshaking process is described as follows: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent).In order to ease your design work, the further explanations of the POC operations and some design hints are given as follows:The buffer register BR is used to hold a character that has been sent via the system bus while that the character is being transferred to the printer. The status register SRis used for two control functions:SR7serves as a ready flag for system bus transfers to BR (like the printer RDY signal for transfers from POC to the printer), and SR0 is used to enable or disable interrupt requests from POC. If SR0=1, then POC will interrupt when it is ready to receive a character (i.e., when SR7=1). If SR0=0, then POC wil