基于vhdl万年历的设计说明书.docxVIP

数字万年历与数字钟的设计一、设计要求数字万年历要求可以任意设定年份月份和日期；当当日时钟走过24时(即0点)后，日期能够自动改变。同样，当每月的最后一天走完后，月份也能够自动显示为下一个月。年份的变化也是如此。时钟计时按照一天24小时计。时钟也可以按照由人工设定当前时间，或者修改当前时间，修改完成后，计时即有当前时间开始。显示方式：日期为2001-11-08，时钟为hh-mm-ss；日期和时钟轮流显示。二、设计原理本设计先用VHDL语言写出需要的各个小模块，并将这些模块进行编译并打包成图形文件，最后将这些图形文件在顶层文件里进行连线，实现具体要求与功能。实验源程序：LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.std_logic_unsigned.ALL;ENTITY onesecond ISPORT (RESET: IN STD_LOGIC; GCLKP1: IN STD_LOGIC; clkout: out std_logic);END onesecond ;ARCHITECTURE Frequency_arch OF onesecond ISSIGNAL Period1S: STD_LOGIC;BEGIN PROCESS( RESET, GCLKP1)VARIABLE Count1 : STD_LOGIC_VECTOR(25 DOWNTO 0); BEGIN IF( GCLKP1EVENT AND GCLKP1=1 ) THEN IF( Count110111110101111000010000000 ) THEN Count1 := 00000000000000000000000000;ELSECount1 := Count1 + 1;END IF;Period1S = Count1(25);-- 1MHz END IF; clkout = Period1S; end process;END Frequency_arch;60进制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt60 isport( clk: in std_logic; ld: in std_logic;da,db:in std_logic_vector(3 downto 0); outa:out std_logic_vector(3 downto 0); outb:out std_logic_vector(3 downto 0); c0: out std_logic);end cnt60;architecture one of cnt60 issignal ma,mb:std_logic_vector(3 downto 0);beginc0=1 WHEN( ma=5 and mb=9 ) else 0 ;process(clk,ld)begin if clkevent and clk=1 thenif ld=1 then ma=da;mb=db; elsif ma=5 and mb=9 thenmb=0000;ma=0000;elsif mb=9 then mb=0000;ma=ma+1;else mb=mb+1; end if; end if;end process;outa=ma;outb=mb;end one;24进制程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt24 isport(clk: in std_logic;ld: in std_logic;da,db:in std_logic_vector(3 downto 0);outa:out std_logic_vector(3 downto 0);outb:out std_logic_vector(3 downto 0);c0: out std_logic);end cnt24;architecture one of cnt24 issignal ma,mb:std_logic_vector(3 downto 0);beginc0=1 WHEN( ma=2 and mb=3 ) else 0 ;process(clk,ld)begin if clkevent and clk=1 thenif ld=1 thenma=da;mb=db; elsif ma=2 and m