基于FPGA的多路答器的设计毕业设计论文.docx

摘要随着计算机技术和电子技术的迅速发展，现在的抢答器的功能越来越强，准确性和可靠性也越来越高。大部分传统的抢答器都是基于数字电路构成的，不仅制作过程复杂，而且可靠性和准确性较低，还有成品面积大，安装、维护困难等问题。近年来电子技术得到迅速发展，使得电子系统的设计者利用EDA软件，就可以独立设计所需的专用集成电路（ASIC）器件，现在利用现场可编辑逻辑门阵列（简称FPGA）制作的抢答器，不仅制作过程简单，而且准确性也更高。本设计的主芯片是EP2C35F672C8，系统由组别判断电路、分频电路、倒计时电路、抢答判别电路、扫描信号产生电路、信号匹配电路和显示电路组成。该抢答器可以容纳四组八位选手同时参与抢答，系统具有清零功能和倒计时功能。经编译和仿真所设计的程序，并下载到开发系统上进行调试验证，最终完成抢答器的设计。关键词：电子设计自动化；可编程逻辑门阵列；抢答器AbstractWith the development of electronic technology andelectronic technology，the Responder is now more powerful, more and more high reliability and accuracy. Most of the previous Responder composed of digital circuits based on the traditional. Complex production process, and the accuracy and reliability is not high, finished area, installation, maintenance difficulties. The rapid development of electronic technology in recent years, Electronic system designers use EDA software, it can be designed independently required special circuit (ASIC) devices. Now design and implementation of the multiplex responder based on FPGA,the production process is not only simple, but accuracy is also higher.The design of the main chip is EP2C35F672C8, the system judgment circuit by a group of the frequency divider circuit, the countdown circuit, answer determination circuit, the scanning signal generating circuit, a signal matching circuit and the display circuit. The Responder can accommodate four groups of eight players to participate simultaneously answer, the system has a clear function and countdown functions. The compilation and simulation of the design process, and downloaded to the development system to debug validation, the final completion Responder design.Key words: EDA；FPGA；Responder1 绪论1.1 前言抢答器在各种智力竞赛中经常被使用到，也有些电视节目利用抢答器来提高节目的可看性，调动观众的参与热情。抢答器要求能准确判断和显示第一抢答信号并进行锁存，为了保证各种智力竞赛、比赛的准确性和公正性，对抢答器的研究有着其重要的意义。1.2抢答器研究的背景与意义现在计算机技术和电子技术正在高速发展，而集成电路的生产工艺也不断提高，这使得电子产品的更新换代越来越快。其中以数字电路系统设计的电路规模更大，集成度更高，而且设计周期较短，灵活性也更强，面对不同的用户，能很方便地修改和迅速升级。现在，EDA（电子设计自动化）技术的广泛应用使得电路的设计者能在开发平台上使用HDL或画电路原理图的方式设计电路，这大大提高了电