第12章 实用电路模块设计PPT.ppt

12.8 等精度频率/相位计设计 12.8.5 相位测试 图12-40 鉴相器EPD的仿真波形 12.9 DDS设计 图12-41 DDS基本结构 12.9 DDS设计 图12-42 相位累加器位宽和采样点关系 接下页 【例12-14】 LIBRARY IEEE; --DDS顶层设计 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS_VHDL IS PORT ( CLK : IN STD_LOGIC; FWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --频率控制字 PWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --相位控制字 FOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END; ARCHITECTURE one OF DDS_VHDL IS COMPONENT REG32B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG10B KX康芯科技 PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER32B PORT ( A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER10B PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT SIN_ROM PORT ( address : IN STD_LOGIC_VECTOR(9 DOWNTO 0); inclock : IN STD_LOGIC ; 接下页 KX康芯科技 q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; SIGNAL F32B，D32B，DIN32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL P10B，LIN10B，SIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); BEGIN F32B(27 DOWNTO 20)=FWORD ; F32B(31 DOWNTO 28)=0000; P10B( 1 DOWNTO 0)=00 ; F32B(19 DOWNTO 0)=00000000000000000000 ; P10B( 9 DOWNTO 2)=PWORD ; u1 : ADDER32B PORT MAP( A=F32B,B=D32B, S=DIN32B ); u2 : REG32B PORT MAP( DOUT=D32B,DIN= DIN32B, LOAD=CLK ); u3 : SIN_ROM PORT MAP( address=SIN10B, q=FOUT, inclock=CLK ); u4 : ADDER10B