调试接口业论文外文文献翻译.docVIP

【原文】CHAPTER 3 Debug Interface The two-wire debug interface allows programming of the on-chip flash, and it provides access to memory and register contents and debug features such as breakpoints, single-stepping, and register modification.The debug interface uses I/O pins P2.1 and P2.2 as debug data and debug clock, respectively, during debug mode. These I/O pins can be used as general-purpose I/O only while the device is not in debug mode. Thus, the debug interface does not interfere with any peripheral I/O pins. Debug Mode Debug mode is entered by forcing two falling-edge transitions on pin P2.2 (debug clock) while the RESET_N input is held low. While in debug mode, pin P2.1 is the debug-data bidirectional pin, and P2.2 is the debug-clock input pin. Debug Communication The debug interface uses a SPI-like two-wire interface consisting of the P2.1 (debug data) and P2.2(debug clock) pins. Data is driven on the bidirectional debug-data pin at the positive edge of the debug clock, and data is sampled on the negative edge of this clock. The direction of the debug-data pin depends on the command being issued. Data is driven on the positive edge of the debug clock and sampled on the negative edge. Figure 3-1 shows how data is sampled. Figure 3-1. External Debug Interface Timing The data is byte-oriented and is transmitted MSB-first. A sequence of one byte is shown in Figure 3-2. Figure 3-2. Transmission of One Byte A debug command sequence always starts with the host transmitting a command through the serial interface. This command encodes the number of bytes containing further parameters to follow, and whether a response is required. Based on this command, the debug module controls the direction of the debug data pad. A typical command sequence is shown in Figure 3-3. Note that the debug-data signal is simplified for the clarity of the figure, not showing each individual bit change. The direction is not explicitly indicated to the