数字电路系设计代码.docVIP

第一讲 FPGA器件介绍，ISE开发环境介绍 第二讲 （1）以一个三位加法器为例介绍开发流程 （2）点亮8个LED led.vhd文件 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity led is Port ( led : out STD_LOGIC_VECTOR (7 downto 0)); end led; architecture Behavioral of led is begin led end Behavioral; led.ucf文件 NET LED[7] LOC=G1; NET LED[6] LOC=P4; NET LED[5] LOC=N4; NET LED[4] LOC=N5; NET LED[3] LOC=P6; NET LED[2] LOC=P7; NET LED[1] LOC=M11; NET LED[0] LOC=M5; (3)按键控制led的亮灭 按下bnt0,LED0亮，再次按下，LED灭，依次下去 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ledbutton is Port ( button : in STD_LOGIC; led : out STD_LOGIC); end ledbutton; architecture Behavioral of ledbutton is signal sled:STD_LOGIC; begin process(button) begin if (buttonevent and button=1) then sled=Not sled; end if; end process; led=sled; end Behavioral; ucf文件 NET button LOC=G12; NET led LOC=M5; NET button CLOCK_DEDICATED_ROUTE=FALSE; 第三讲 (4)让LED0灯光1s闪烁一次 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ledflash is Port ( clk : in STD_LOGIC; led : out STD_LOGIC); end ledflash; architecture Behavioral of ledflash is signal clk1s:STD_LOGIC:=0; begin process(clk) variable cnt:INTEGER:=0; begin if (clkevent and clk=1) then if (cnt then cnt:=0; clk1s = NOT clk1s; else cnt:=cnt+1; end if; end if; end process; led=clk1s; end Behavioral; UCF文件 NET clk LOC=B8; NET led LOC=M5; NET clk CLOCK_DEDICATED_ROUTE=FALSE; （5）流水灯 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity flashlight is Port ( clk : in STD_LOGIC; led : out STD_LOGIC_VECTOR (7 downto 0)); end flashlight; architecture Behavioral of flashlight is signal clk1s:STD_LOGIC:=0; signal ledout:STD_LOGIC_VECTOR (7 downto 0): component div is Port ( clk : in STD_LOGIC; led : out STD_LOGIC); end component; begin div1: div port map(clk=clk, led=clk1s); led=ledout; process(clk1s) begin if clk1sevent and clk1s=1 then ledout=ledout(6 downto 0)ledout(7); end if; end process; end Behavioral; --分频模块 library IEEE