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Dynamic Instruction Issue动态指令的问题
7. Microarchitecture of Superscalars (5)Dynamic Instruction Issue Dezs? Sima Fall 2006 * ? D. Sima, 2006 Overview 1 The principle of dynamic instruction issue 2 Design space 2.1 Overview 2.2 Types of issue buffers 2.3 Operand fetch policies 4 Implementation of dynamic instruction issue in superscalars 4.1 The introduction of dynamic instruction issue 4.2 Basic implementation schemes 3 Principle of operation of dynamic instruction issue 3.1 Dispatch bound operand fetching 3.2 Issue bound operand fetching 5 Case examples 1. Principle of dynamic instruction issue (1) Aim: To eliminate the issue bottleneck of early (first generation) supercalars 1. Principle of dynamic instruction issue (2) The issue bottleneck (b): The issue process (a): Simplified structure of the mikroarchitecture assuming unbuffered issue Figure 1.1: The principle of dynamic instruction issue Icache I-buffer Instr. window (3) Decode, check, issue Dependent instructions block instruction issue EU Issue EU 1. Principle of dynamic instruction issue (3) Figure 1.2: Principle of dynamic instruction issue (b): The issue process (a): Simplified structure of the mikroarchitecture assuming buffered issue (shelving) Eliminating the issue bottleneck Dynamic instruction issue (shelving, buffered issue) Layout of the issue buffers Scope of dynamic instr. issue Instruction issue scheme Dynamic instruction issue Operand fetch policy 2. Design space of dynamic instruction issue 2.1 Overview Types of issue buffers 2.2 Types of issue buffers Reservation stations (RS) Issue buffers in the ROB Types of issue buffers Individual RSs Central RS Group RSs RS FX EU RS FP EU FX EU RS FP EU FX EU FP EU Power1 (1990) PowerPC 603 (1993) PowerPC 604 (1995) Power4 (2001) Power5 (2004) K5 (1995) K7 (1999), K8 (2003) RS FX EU FX FX EU RS FX EU FP FX EU ES/9000 (1992) Power2 (1993) R10000 (1996) PM1(Sparc64)(1995) Alpha 21264 (1997) Pentium Pro (1995) Pentium II (1997) Pentium I
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