Part II Lecture 5 Single-cycle control and datapath：第二部分讲座5单周期控制和数据通路.pptVIP

CS1104-p2-6 CS1104 Computer Organization Part 2 CS1104 – Computer Organization PART 2: Computer Architecture Lecture 5 Single-Cycle Control and Datapath Topics Building a datapath support a subset of the MIPS-I instruction-set A single cycle processor datapath all instruction actions in one (long) cycle A multicycle processor datapath each instructions takes multiple (shorter) cycles Control: microprogramming The MIPS Instruction Formats All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction Datapath and Control The Processor: Datapath Control Were ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j Generic Implementation: use the program counter (PC) to supply instruction address get the instruction from memory read registers use the instruction to decide exactly what to do All instructions use the ALU after reading the registers Why? memory-reference? arithmetic? control flow? More Implementation Details Abstract / Simplified View: Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential) State Elements Unclocked vs. Clocked Clocks used in synchronous logic when should an element that contains state be updated? An unclocked state element The set-reset (SR) latch output depends on present inputs and also on past inputs Latches and Flip-flops Output is equal to the stored value inside the element(dont need to ask for permission to look at the value) Change of state (value) is