基于FPGA的电梯控制.docVIP

题目： 基于FPGA的电梯控制器设计 摘 要 本设计主要介绍了基于FPGA设计的五层电梯控制器，采用VHDL语言进行编译，并进行了电路综合和仿真。由于普通电机不能准确起动和停止和控制旋转角度等缺陷，本设计电机采用三相步进电机作为动力源。根据当前电梯内外两个控制系统收集电梯内外的人员流向并将数据汇总交由中央运算控制器运算产生下一个步骤电梯将要前往的楼层，并将相关楼层数据交由专门的步进电机控制器。步进电机控制器控制电机到达指定楼层。 本设计采用VHDL，源程序Altera公司的Quartus II软件仿真。运用有限状态机的设计方法，设计了两个进程相互配合，状态机进程作为主要进程，信号灯控制进程作为辅助进程。在主进程中定义了7个状态，分别是“stopon1”“dooropen”“doorclose”“doorwait4”“up”“down”和“stop”,在电梯时钟的触发下，通过当前状态和信号灯信号判定下一状态。信号灯控制进程中，信号灯存储按键请求情况，它的熄灭是由状态机进程中传出的信号来控制。 关键字：FPGA、VHDL、电梯控制器、EDA实验开发系统 Based on the five-layer elevator controller FPGA research Abstract：This design introduces FPGA design based on five elevator controller,compiled with VHDL language, and make the circuit synthesis and simulation.The controller follows the direction of the principle of priority, to provide three floors of the passenger service multiple users, and indicates the operation of the lift. General Motors can not accurate due to start and stop and control defects such as rotation, the design of the electrical use of three-phase stepper motor as the motive power source. This design which uses VHDL simulated by Altera’s Quartus II software. I use method named finite state machine which two processes complement each other. The state machine process act as the main process, and the signal control process act as a assistant. Seven states were defined in the main process, namely “stopon1” “dooropen” “doorclose” “doorwait4” “up”“down” and “stop”. Triggered by the lift’s clock, the next state is determined by the current state and the signal. In signal control process, registers keep input value, and lamps black out when the control process, registers keep input value, and lamps black out when the control signal in the main process is high value. Keywords: FPGA, VHDL, Elevator Controller, EDA experiment development syste PAGE 25 谢 辞 大学生活已经快结束，在本专业的学习中使我掌握了不少专业知识，锻炼了自己。毕业设计可以说是我大学学习的总结和体现，在指导老师刘苹的指导和帮助下，我完成了这篇毕业设计。他热心的帮助和循循善诱的指导深深感动了我。这篇设计和所有教育过我的老师也是分不开的，没有他们的传授的知识我也不可能完成这个的课题。我无论是在课程学习阶段，还是在论文的选