基于MA型分布式算法高阶FIR滤波器设计及其FPGA实现.docVIP

基于MA型分布式算法高阶FIR滤波器设计及其FPGA实现 　　摘 要: 　　针对利用现有分布式算法在FPGA上实现高阶FIR滤波器时,存在资源消耗量过大和运行速度慢等问题,提出一种新型高阶FIR滤波器的FPGA实现方法。首先综合采用多相分解结构、流水线等技术对高阶FIR滤波器进行降阶处理,然后采用提出的基于二输入开关和加法器对的分布式算法结构(MA型DA结构)实现降阶后的FIR滤波器。利用ISE10.1在Xilinx Xc2vp30??7ff896 FPGA开发板上实现了一系列8阶到256阶的串行和并行结构FIR滤波器。实验结果表明，该方法有效地减少了系统的资源消耗,提高了系统的时序性能。 　　?ス丶?词: 　　FIR滤波器;MA型分布式算法;多相分解;流水线;现场可编程门阵列 　　?ブ型挤掷嗪?: 　　TP302 　　文献标志码:A 　　英文标题?? 　　High??order FIR filter design on FPGA using MA distributed algorithm 　　?び⑽淖髡呙? 　　LI Fei, ZENG Yi??cheng, AN Chao??qun, YU Yun??xia 　　?び⑽牡刂?( 　　Department of Photoelectric Engineering, Xiangtan University, Xiangtan Hunan 411105, China 　　英文摘要)?? 　　Abstract: 　　Concerning the problems of too much resource consumption and too low processing speed, a new high??order FIR filter targeted Field Programmable Gate Array (FPGA) was proposed. Firstly, polyphase decomposition architecture and pipeline technology were adopted to decompose high??order FIR filter into low??order ones, and then the proposed MA distributed algorithm architecture was used to implement the decomposed filters in the method. A series of serial and parallel FIR filters which order from 8 to 256 were implemented by ISE10.1 targeted Xilinx Xc2vp30??7ff896 FPGA device. The experimental results show that the proposed method effectively reduces the system resource consumption and improves the timing performance of the system. 　　英文关键词??Key words: 　　FIR filter; MA distributed algorithm;polyphase decomposition; pipeline technology; Field Programmable Gate Array (FPGA) 　　 　　0 引言?? 　　有限冲激响应（Finite Impulse Response， FIR）滤波器是数字信号处理系统的重要组成部分,基于MAC结构的FIR滤波器的现场可编程门阵列（Field Programmable Gate Array， FPGA）实现,只需乘法器、加法器和移位寄存器即可,但直接使用FPGA上的硬件乘法器不但造成资源浪费,而且还会影响滤波器的性能和速度[1],为此,近年来人们提出了几种无乘法器结构[2-3]。按对滤波器系数的操作处理,这些方法可以分为两类:一是把系数转换为比普通二进制码更有效的硬件码制(如最常用CSD编码),即把滤波器系数转换为CSD码,通过移位和求和实现乘法操作[2-3];二是把系数所有的可能组合存入查找表中,然后根据采样值确定滤波器的输出,最具有代表性的就是分布式算法(Distributed Arithmetic,DA)[4-9]。?? 　　Croisie等人[4]提出的DA,是一种利用查找表(Look Up Table, LUT)代替乘法器的算法,