毕业论文基于fpga的四路抢答器设计说明书.doc

PAGE 摘 要 本文介绍了以FPGA为基础的四路抢答器的设计，此次设计是一个有4组抢答输入，并具有抢答计时控制，按键消抖以及积分显示等功能的通用型抢答器。主持人有4个按键控制，可以进行开始抢答，对各抢答小组成绩进行相应加减操作以及所有积分重置。此次设计程序使用verilog语言编写，并且使用modelsim进行相关仿真，最后在FPGA开发板上烧录程序进行实际操作演示实现了相应功能，达到了此次设计的目的。本设计采用FPGA来做增强了时序控制的灵活性，同时由于FPGA的IO端口资源丰富，可以再本设计基础上稍加修改可以重复设计出具有多组输入的抢答器。 关键字：按键消抖；显示；仿真；四路抢答； Abstract In this paper, the design of four channel responder based on FPGA is proposed. The design contains four channel input, and also it has timing function, button-stop-shaking function, score display function. And the result of the design is a universal responder. The host has four buttons to control, in order to start response, add or sub the scores for each group and clear all group scores. The design program uses verilog language to write software. And modelsim is used to simulate the function on computer. At last the actual design results are demonstrated on the FPGA development board, and the functions are well veified. The result achieves the purpose of the design. The design uses FPGA to enhance the flexibility of timing control. At the same time because of IO port resoures in FPGA are much rich, if you want to design more channels responder, you just only repeat design on the basic of the design which is slightly modified. Keywords: button-stop-shaking; display; simulate; four channel responder; 目 录 TOC \o 1-3 \f \h \z \u TOC \o 1-3 \h \z \u HYPERLINK \l _Toc326094348 1 引言 PAGEREF _Toc326094348 \h 4 HYPERLINK \l _Toc326094349 2 FPGA原理及其相关工具软件的介绍 PAGEREF _Toc326094349 \h 5 HYPERLINK \l _Toc326094350 2.1 FPGA开发过程与应用 PAGEREF _Toc326094350 \h 5 HYPERLINK \l _Toc326094351 2.1.1 FPGA发展历程及现状 PAGEREF _Toc326094351 \h 5 HYPERLINK \l _Toc326094352 2.1.2 FPGA工作原理 PAGEREF _Toc326094352 \h 6 HYPERLINK \l _Toc326094353 2.1.3 FPGA开发流程 PAGEREF _Toc326094353 \h 6 HYPERLINK \l _Toc326094354 2.2 Quartus II软件 PAGEREF _Toc326094354 \h 7 HYPERLINK \l _Toc326094355 2.3 Simulink软件 PAGEREF _Toc326094355 \h 8 HYPERLINK \l _Toc326094356 2.3.1 代码仿真 PAGEREF _T