一种基于时延配置表的FPGA静态时序分析算法-太赫兹科学与电子.PDFVIP

第 16 卷 第 4 期 太赫兹科学与电子信息学报 Vo1．16，No．4 2018 年 8 月 Journal of Terahertz Science and Electronic Information Technology Aug．，2018 文章编号：2095-4980(2018)04-0735-07 一种基于时延配置表的 FPGA 静态时序分析算法 喻 伟，陈恩耀，马海燕，祝周荣，宋雷军，王永孟 (上海航天电子技术研究所，上海 201109) 摘 要 ：为减小现场可编程门阵列(FPGA) 关键路径的延时误差，提出一种基于时延配置表的 静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑 了工艺角变化对延时参数的影响，同时在时序分析过程中，通过分析路径始节点与终节点的时钟 关系，实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明，与公认的基于查找表的项 目评估技术(PERT) 算法和VTR 算法相比，关键路径延时的相对误差平均减少了8.58% 和6.32% ，而 运行时间平均仅增加了19.96%和9.59% 。 关键词 ：现场可编程门阵列；静态时序分析；配置表；关键路径 中图分类号 ：TN702 文献标志码 ：A doi ：10.11805/TKYDA201804.0735 A FPGA static timing analysis algorithm based on delay collocation table YU Wei，CHEN Enyao，MA Haiyan，ZHU Zhourong，SONG Leijun，WANG Yongmeng (Shanghai Aerospace Electronic Technology Institute，Shanghai 20 1109，China) Abstract： A static timing analysis algorithm is proposed, which applies the delay collocation table, to reduce the relative error of critical path delay in Field Programmable Gate Array(FPGA). Based on the collocation table model of the logic element delay and interconnect delay, the algorithm takes into account the process corner variations effect on delay parameters. In timing analysis phase, by computing the clock relationship between source node and sink node, path searching and delay calculating in multi-clock domains are achieved. Experimental results demonstrate that the relative error of critical path delay is reduced by 8.58% and 6.32% respectively on average when compared with the Program Evaluat ion and Review Technique(PERT) and the VT