F创新及持续学习之能力培训教材.pptVIP

* 4-bit binary counter w/ parallel load Fig. 6.14 Four-bit binary counter with parallel load * Fig. 6.14 Four-bit binary counter with parallel load (cont.) async count load load c_en c_en A0 * Generate any count sequence: E.g.: BCD counter ? Counter w/ parallel load Fig. 6.15 Two ways to achieve a BCD counter using a counter with parallel load * 6-5 Other Counters Counters: can be designed to generate any desired sequence of states Divide-by-N counter (modulo-N counter) a counter that goes through a repeated sequence of N states The sequence may follow the binary count or may be any other arbitrary sequence * n flip-flops ? 2n binary states Unused states states that are not used in specifying the FSM may be treated as don’t-care conditions or may be assigned specific next states Self-correcting counter Ensure that when a ckt enter one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation. ? Analyze the ckt to determine the next state from an unused state after it is designed * An example Two unused states: 011 111 The simplified flip-flop input eqs: JA = B, KA = B JB = C, KB = 1 JC = B?, KC = 1 * The logic diagram state diagram of the ckt Fig. 6.16 Counter with unsigned states The simplified flip-flop input eqs: JA = B, KA = B JB = C, KB = 1 JC = B?, KC = 1 * Ring counter: a circular shift register w/ only one flip-flop being set at any particular time, all others are cleared (initial value = 1 0 0 … 0 ) The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals. * A 4-bit ring counter A2 A2 A1 A0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 Fig. 6.17 Generation of timing signals * Application of counters Counters may be used to generate timing signals to control the sequence of operations in a digital system. Approaches for generation of 2n timing signals 1. a shift register w/ 2n flip-flops 2.