实验三组合电路设计（一）.docVIP

实验三 组合电路设计（一） 1．实验目的 掌握设计组合逻辑电路的方法。 通过开发CPLD来实现组合逻辑电路的功能。 2．示例 （1）数选器74153的VHDL描述。 源程序: Library ieee; Use ieee.std_logic_1164.all; Entity mux4 is Port(d0,d1,d2,d3:in std_logic; St,a,b:in std_logic; y:out std_logic); End; Architecture bhv of mux4 is Signal co:std_logic_vector(1 downto 0); Begin Co=ba; Process(st,a,b) begin If (st=’1’) then Case co is When”00”=y=’d0’; When”01”=y=’d1’; When”10”=y=’d2’; When”11”=y=’d3’; When others=y=’0’; End case; End if; End process; End; (2) 代码转换 要求：输入为8421BCD码，输出为2421码,如表4-3-1所示。 源程序： Library ieee; Use ieee.std_logic_1164.all; Entity dmzh is Port(a:in std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); End; Architecture rtl of dmzh is Begin Process(a) Begin Case a is When”0000”=y=”0000”; When”0001”=y=”0001”; When”0010”=y=”0010”; When”0011”=y=”0011”; When”0100”=y=”0100”; When”0101”=y=”1011”; When”0110”=y=”1100”; When”0111”=y=”1101”; When”1000”=y=”1110”; When”1001”=y=”1111”; When others=y=”ZZZZ”; End case; End process; End; (3) 8线.—3线编码器74-148的设计 源程序： Library ieee; Use ieee.std_logic_1164.all; Entity yxbm8_3 is Port(i:in std_logic_vector(7 downto 0); St:in std_logic; Y:out std_logic_vector(2 downto 0); Ys,yex:out std_logic); End; Architecture bhv of yxbm8_3 is Begin Process(i,s) Begin If st=’1’ then Y=”111”; Ys=’1’; Yex=’1’; Else If I(7)=’0’ then Y=”000”; Ys=’1’; Yex=’0’; Elsif I(6)=’0’ then Y=”001”; Ys=’1’; Yex=’0’; Elsif I(5)=’0’ then Y=”010”; Ys=’1’; Yex=’0’; Elsif I(4)=’0’ then Y=”011”; Ys=’1’; Yex=’0’; Elsif I(3)=’0’ then Y=”100”; Ys=’1’; Yex=’0’;