查询SN74LVC1G126供应商.PDFVIP

查询SN74LVC1G126供应商 SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES224C – APRIL 1999 – REVISED FEBRUARY 2000 EPIC (Enhanced-Performance Implanted DBV OR DCK PACKAGE CMOS) Submicron Process (TOP VIEW) Ioff Feature Supports Partial-Power-Down Mode Operation OE 1 5 VCC A 2 Supports 5-V VCC Operation GND 3 4 Y Package Options Include Plastic Small-Outline Transistor (DBV, DCK) Packages description This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G126 is a single bus driver/line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, W preventing damaging current backflow through the device when it is powered down.