电子科技大学《数字逻辑设计及应》lec17-chap 7.pptVIP

* Summaries of Latch and Flip-Flop Latch: output changes when CLK is asserted Flip-Flop: output only changes when clock changes S-R Latch/FF, D Latch/FF, J-K FF, T FF Logic Symbol Function Table Transition Table Characteristic Equ. Excitation tables State Diagram EN Jin. UESTC Digital Logic Design and Application * Digital Logic Design and ApplicatonLecture #17 Latches and Flip-Flops UESTC, Spring 2013 * 再谈串行输入加法器的实现 Q D Q C X Y CI Si Ci+1 Xi Yi Ci S CO CLK 暂存 X Y CI CO S Ci+1 Si Xi Yi Ci 时钟控制 电平有效还是边沿有效？ 串行输入、串行输出 注意：时钟同步 Iterative Vs. Sequential *