32位微处理器一级指令cache中sram的设-集成电路工程专业毕业论文.docxVIP

东南大学工程硕士学位论文 东南大学工程硕士学位论文 万方 万方数据 万方数据 万方数据 II AbstractWith Abstract With the increasement ofintegrated scale ofprocessor,the capacity ofcache based Static Random Access Memory(SRAM)technology is rapidly increasing and the proponion ofits in System Chip(SoC)is increasing year by year，thus the performance of cache haS significallt 1mpact on‘he performance of Central Processing Unit(ceu)．The main appIic撕on of cache is to smoom the speed difference between processor and off-chip memory,therefore SRAM is typicallv used for the design of caehe in order to obtain higher speed and the custom design of high． speed low-power SRAM is very favorable for the improvement ofCPU DerIl0兀nance． Firstly,by analyzing read and write operations of SRAM memory cell，this thesis obtains the limits of transistors in storage unit and provides the specific size of the memory cell uSed in the SRAMs·In order to shorten the pulse width of wordline and reduce the power consl】mDtion of bitline during read and write operations，self-time technique is adopted to control出e read and write operations of Data SRAM．Then，this thesis introduces novel latch type sense锄D1ifier whjch improve the speed of Data SRAM and reduce the power consumption du咖g read operation well np·CMOS dynamic Tag comparator which efrectively accelerate出e speed of comparison of Tags by separating the upper address and the lower address．Then．the layout design ofLl instruction cache is introduced in this thesis and the overall layout ofSRAM is provided well．Finally,a simulation of read and write operations is conducted to verify the funcdonal correctness and timing compliance of the SRAMs． The capacity of Data SRAM，Tag SRAM and Status SRAM designed in mis thesl’s respectively 32KB，3KB and 128B．At 1．0V supply voltage，the simulation resuIts based TSMC 65mn process show that the maximum read write delay of Tag SRAM，Status SRAM and Data SRAM is 0．479ns meeting the design requirements of 0．5ns．In addition，the operating疗equency of SRAM