epon系统中前向纠错技术的研究及其编译码器的lsi设计.docxVIP

优秀毕业论文 精品参考文献资料 Abstract Abstract EPON(Ethernot Passive Optical Network)is designed to achieve Ethernct aCCeSS witll PON topologies and it is a new broadband optical fiber access technology．As a mature error control coding technology，FEC(Forward Error Correction)is used creatively in EPON by IEEE 802．3ah EFM(Ethemet For the First Mile)task force． This paper firstly summarizes EPON system and its research status at home and abroad，the application significance of FEC in EPON is also introduced．Then the application principle and implementation mechanism of FEC in EPON is studied in detail，the basic theory of RS code used in EPON’S FEC is expounded and the algorithm of encoding and decoding of RS and meir implementation principle are analyzed．The top-down and modular design method adopted in the VLSI design of RS(255，2391 encoder and decoder is discussed mainly，the general design structure and design scheme are given．Furthermore，in order to improve the system speed by using pipeline technology and decrease design complexity of encoder and decoder by optimizing the structure of variable finite field multiplier．Meanwhile the design of RS(255，23 9 1 encoder and decoder is describcd in Vcrilog HDL at RTL(Register Transfer Level)level．Subsequently，the functional simulation and verification is carried out by Synopsys Inc tool VCS，then the RTL code of encoder and decoder is synthesized using a Athcros 0．1 3gm CMOS standard cell library by Synopsys Inc tool DC(Design Compiler)， at the same time，timing violations are eliminated in RTL design．Finally,the analysis of functional simulation results verifies the accuracy of the design of RS(255，239)encoder and decoder，the highest normal working clock fiequency of this design can be up to 277MHz and it fully meets and exceeds 125MHz performance requirement of EPON system． Keyword：EPON FEC RS encoding and decoding Finite field multiplier VLSI  西安电予jI斗技大学 学位论文独创性(或创新l生)声明 秉承学校严谨的学风和优良的科学道德，本人声明所呈交的论文是我个人在 导师指导下进行的研究工作及取得的研究成果。尽