基于SPARC架构面向确定性重演的多核访存竞争记录方法的分析-计算机科学与技术专业论文.docxVIP

Abstract Nowadays, with the continuous advancement of electronic and information technology, the people’s demand for high-performance computers is growing more and more stronger. Limited by the development of material, processor manufacturing, power consumption, heat dissipation and some other reasons, the processor design pattern of increasing the frequency of CPU to increase the processor performance has encountered difficulties. Integrating the cores onto a single integrated circuit die has become the development of processor design pattern. However, at the same time, it also brought a number of new problems. While having not been arisen in single processor system, the nondeterministic multi-core processor system caused by memory race is one of the new problems, and this problem is becoming one of the hot areas of computer multi-core structure and parallel computing. The existing multi-core cache coherence protocols in shared memory multi-core processor system can effectively prevent the data inconsistency during program executing, but the order of access between multiple threads is out of control. That is, if a multi-thread program executing in a shared memory multi-core processor system and does not take strict synchronization measures, it may cause the bugs of the violation of expected program execution sequences. That is, under the circumstance of repeatedly executions, even if the same inputs may cause the different outputs. To solve this problem, the technique of deterministic multi-core replay has been proposed, and this would ensure the outputs will be the same. Based on the understanding of the SPARC architecture, cache coherence protocols and aiming at solving the problems of the nondeterministic shared memory multi-core processor system of SPARC architecture in CMP architecture , this paper describes a memory race recording method in deterministic multi-core replay based on SPARC architecture——ERTR method. The ERTR method uses the idea of sl