基于VHDL的电子表设计.pptVIP

component counter port( clk,load:in std_logic; buffertime: in std_logic_vector(23 downto 0); time:out std_logic_vector(23 downto 0) ); end component; component alarmreg port( clk,alarmload:in std_logic; buffertime:in std_logic_vector(23 downto 0); alarmtime:out std_logic_vector(23 downto 0) ); end component ; component bell port( clk,houralarmon,alarmon:in std_logic; alarmtime,time:in std_logic_vector(23 downto 0); alarm_signal:out std_logic ); end component; signal buffertime,time,alarmtime:std_logic_vector(23 downto 0); signal iscount,alarmload,timeloa