快速高稳定性九管SRAM单元电路分析.pdfVIP

Abstract Abstract All kinds of memory will be embedded in today’s SoC system in order to improve the system’s performance; especially the static random access memory （SRAM）.It will be the chief factor when we think about how to select the memory because SRAM is compatible to the standard CMOS process. These memorys possess the great proportion of the whole chipset both in the energy consumption and in the chipset area, so the chipset performance is decided by these memory performance.The high performance memory design is most important for SoC system. In a conventional 6T SRAM cell, in read operation, the data storage nodes are directly accessed through the access transistors connected to the bit lines. Moreover, voltage distribution between access transistors and inverters heightens the 0 voltage level So the data is vulnerable to external noise during read operation. 7T SRAM cell is aiming at improving the stability of 6T SRAM cell. The data storage nodes are isolated from the bit lines, and voltage distribution is eliminated, so 7T SRAM cell becomes more stable than 6T SRAM cell. However, 7T SRAM cells weak write capability is a critical problem. In this paper, a new 9T SRAM cell is researched. The new 9T SRAM cell solves the question which is the stability of 6T SRAM cell and the 7T SRAM cell ’s write capability commendably. Finally, these SRAM cell are simulated by HSPICE in read delay, write margin, static noise margin, leakage and the dynamic power consumption. The results show that the 9T SRAM cell has much better stability and high read speed. Keywords: SRAM cell 9T Stability SNM Leakage